Method for forming patterns aligned on either side of a thin film

ABSTRACT

A method for forming patterns which are aligned on either side of a thin film deposited on a substrate. The method includes depositing a first pattern layer on the thin film which may occur before or after the local etching of the thin film to form a first marking. The method includes etching the first pattern layer in order to form a first pattern and depositing a first bonding layer for covering the first marking and the first pattern. The method may include suppressing the substrate as well as etching the first bonding layer to form a second marking at the location of the first marking. The method includes depositing a second pattern layer, and etching the second pattern layer to form the second pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority based on International PatentApplication No. PCT/FR2003/050179, entitled “Method for Forming PatternsAligned on Either Side of a Thin Film” by Maud Vinet, Simon Deleonibus,Bernard Previtali and Gilles Fanget, which claims priority of FrenchApplication No. 02/15980 filed on Dec. 17, 2002, and which was notpublished in English.

TECHNICAL FIELD AND PRIOR ART

The invention relates to a method for forming aligned patterns on eitherside of a thin film.

The invention more particularly applies to the manufacturing ofcomponents and three-dimensional micro-systems such as for exampledigital circuits of the memory circuit type.

Generally, in microelectronics technology on a semiconductor, markingsare used for achieving alignment of patterns (transistor gates, metalcontacts, metallization levels, etc.). These markings are used both inthe case of optical lithography and in the case of electroniclithography.

In the case of electronic lithography, the alignment markings aregenerally square holes with small dimensions (for example, a surface of8 μm² and a depth of 800 nm) provided in an insulation oxide whichinsulates the different components. They are read by the difference inintensity between electrons backscattered by the holes and thosebackscattered by the surface.

In the case of substrates of silicon on an insulator (SOI), thealignment markings for optical lithography are made in a substrate whichis found under a buried oxide. In a first phase, etching of thesemiconductor thin film which is found above the buried oxide is carriedout, and in a second phase, the buried oxide is etched, in order toexpose a large substrate surface. The markings are then directly etchedin the substrate.

In order to form aligned patterns on both faces of a semiconductor thinfilm, it is necessary to position the patterns made on one facerelatively to the patterns made on the other face.

According to the known art, in the case of optical lithography, makingcircuits having patterns on both faces of active silicon film, leads toan operation during which the original substrate in which the markingsare etched, is removed. The markings therefore disappear with thesubstrate. In the case of electronic lithography, the markings made onan insulation oxide are filled with smoothing oxide. Upon removing theburied oxide, they are also consumed as all their surroundings are inoxide. In both cases, the markings which are used for positioning thepatterns on a first face are totally removed. New markings have then tobe created for making patterns on the second face. The markings createdon the second face now can no longer be aligned with the patterns of thefirst face.

Different methods have been suggested in order to avoid this drawback.

Patent Application EP 513684 discloses alignment markings for achievingresumptions of contact on the rear face of a substrate. For this, afield area is etched in a silicon substrate. The substrate is thencovered with insulator. The alignment markings are etched in the fieldarea whereas the contact holes are etched in the area where the patternsshould be formed. A metal layer is then deposited, and then etched inorder to form the alignment markings and the holes of contacts. The rearface of the substrate is then thinned down until the alignment markingis found which allows the contact hole to be found again. It is thenpossible to again find on the rear face the position of patterns made onthe front face. This technique however has several drawbacks, i.e.:

-   -   obligation of using metal materials,    -   obligation of keeping the same substrate,    -   making essentially local structures (i.e., located at specific        locations) on the rear face and therefore the impossibility of        using the whole rear face (for example, it is not possible to        perform ion implantation).

Another known method discloses an alignment of circuits in threedimensions. At the start, one has two substrates to be aligned. On thefirst substrate, the alignment markings are made at the cutting pathsfor example. At the second substrate, a hole is made which correspondsto the width of the cutting path, this hole then being filled with aninsulating layer which is flattened. Both substrates are then bondedtogether by taking care to align the hole and the cutting path with thehelp of an infrared microscope. Next, the rear face of the secondsubstrate is removed as far as the insulating layer which allowed thehole to be filled and the alignment marking is read with a microscope. Adrawback of this method is the inadequacy of the precision of thealignment which is obtained with the infrared microscope (≈1 μm).

The invention does not have the aforementioned drawbacks.

DISCUSSION OF THE INVENTION

Indeed, the invention concerns a method for forming aligned patterns oneither side of a thin film deposited on a substrate, the methodcomprising local etching of the thin film so as to form a first marking,characterized in that it comprises:

-   -   depositing a first pattern layer on the thin film, the        deposition of the first pattern layer preceding or following the        local etching of the thin film,    -   a first lithography step for defining a first pattern location,        with alignment of the first pattern location relatively to the        first marking,    -   local etching of the first pattern layer in order to form a        first pattern,    -   depositing a first bonding layer for covering the first marking        and the first pattern,    -   turning over the obtained structure following the deposition of        the first bonding layer,    -   suppressing the substrate,    -   a step for etching the first bonding layer in order to form a        second marking at the location of the first marking,    -   a step for depositing a second pattern layer,    -   a second lithography step for defining a second pattern        location, with alignment of the second pattern location        relatively to the second marking, and    -   a step for etching the second pattern layer in order to form the        second pattern.

According to a further feature of the method according to the invention,turning over the structure is followed by a bonding step for bonding thefirst bonding layer with a second bonding layer which covers a transfersubstrate.

According to still a further feature of the method of the invention, asthe first and second bonding layers are oxide layers, bonding ismolecular bonding.

According to still a further feature of the method of the invention, thesecond marking is transferred into the transferred substrate.

According to still a further feature of the method of the invention,local etching of the first and second pattern layers is plasma etching.

According to still a further feature of the method of the invention, thefirst and second pattern layers are layers of polycrystalline silicon ormetal, or nitride, or silicon, or silica, or High-K material.

According to still a further feature of the method of the invention, thethin film is a semiconductor thin film.

According to still a further feature of the method of the invention, thesemiconductor thin film is silicon, gallium arsenide or SiGe film.

According to still a further feature of the method of the invention,local etching of the semiconductor thin film is either wet chemicaletching or anisotropic plasma etching.

According to still a further feature of the invention, the methodcomprises a step for forming a first gate oxide layer between thesemiconductor thin film and the first pattern layer and the step fordepositing the second pattern layer is preceded by the deposition of asecond gate oxide layer on the semiconductor thin film.

According to still a further feature of the method of the invention, thefirst pattern and the second pattern are transistor gates.

According to still a further feature of the method of the invention, thethin film is a metal thin film.

According to still a further feature of the method of the invention, themetal thin film is a TiN or W film.

According to still a further feature of the method of the invention, thefirst and second lithography steps are optical or electronic lithographysteps.

According to still a further feature of the invention, the methodcomprises forming a buffer layer buried between the thin film and thesubstrate.

According to still a further feature of the method of the invention, theburied buffer layer is a SiO₂, SiGe or Ni₃N₄ layer.

SHORT DESCRIPTION OF FIGURES

Other features and advantages of the invention will become apparent uponreading a preferential embodiment made with reference to the appendedfigures wherein:

FIGS. 1-11 illustrate different steps of a first embodiment of themethod for forming aligned patterns according to the invention;

FIGS. 12 and 13 illustrate an alternative of the first embodimentillustrated in FIGS. 1-11;

FIGS. 14-20 illustrate different steps of a second embodiment of themethod for aligning patterns according to the invention.

On all the figures, the same references designate the same components.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

More particularly, the invention will be described in the case ofalignment of gates of transistors located on either side of a thin filmof silicon.

Generally, as already mentioned above, the invention concerns thealignment of any type of patterns (gates, sources, drains, metalinterconnections, contacts, etc.) located on either side of asemiconductor or metal thin film.

FIGS. 1-11 illustrate different steps of a first embodiment of themethod for forming aligned patterns according to the invention.

FIG. 1 illustrates an SOI (Silicon On Insulator) type structureconsisting of a stack of layers deposited on a substrate 1, i.e.: aburied buffer layer 2, a thin silicon layer 3, a first gate oxide layer4, and a first pattern layer 5. Two areas may be distinguished in theSOI structure: a first area A in which the markings will be made, and asecond area B in which the patterns aligned with the markings will bemade.

The first pattern layer 5 has chemical etching selectivity relatively tosilicon oxide. As this will appear subsequently, layer 5 is a layer inwhich the first pattern is formed. Generally, the first pattern layer 5may for example be a layer of polycrystalline silicon, of metal, ofsilicon nitride (Si₃N₄), a High-K (also known as High-K dielectric)material or of gate insulator topped with a stack of gate layers.

A resin layer 6 is first of all deposited on the first pattern layer 5.The resin layer 6 is locally etched in order to expose in the A area, acavity 7 which defines the position of an alignment marking (cf. FIG.2).

Anisotropic plasma etching of the layer 5, of the first gate oxide layer4 and of the thin film 3 of silicon, is then carried out to form amarking 8. This anisotropic plasma etching step is followed by a wetchemical etching step or an anisotropic plasma etching step selectivewith respect to the silicon which transfers the marking 8 as far as intothe buried buffer layer 2 (cf. FIG. 3). The resin layer 6 which belongsto the B portion of the SOI structure provides protection of the layer 5of the B portion during the etching operation.

A resin layer 10 is then deposited in order to partially fill themarking 8 (cf. FIG. 4). An optical or electronic lithography step thenallows the location 9 of a first gate to be defined. During thislithography step, the location 9 of the first gate is aligned on themarking 8. The resin layer 6 located in the B portion of the structureis then insulated by a lithography method and developed in order todefine the location of the patterns to be etched. The layer 5 is thenetched, for example by plasma etching, at locations where the resin hasdisappeared, in order to make a first gate 11 covered with a resin layer12 (cf. FIG. 5). The resin layer 12 is then removed. A first bondingoxide layer 13 is then deposited, for example by spraying or by chemicalvapour deposition, commonly called CVD, in order to fill the space whichdefines the marking as well as the etched areas which surround the gate(cf. FIG. 6). The first bonding oxide layer 13 is then flattened. Theobtained structure following the operation for depositing and smoothingthe layer 13 is then turned over and the free face of the layer 13 isbonded, by molecular bonding (oxide on oxide), onto a second bondingoxide layer 14 which covers a transfer substrate 15 (cf. FIG. 7).

The silicon substrate 1 is then removed by rectification followed bychemical etching, for example by TMAH (Tetra Methyl Ammonium Hydroxide)etching, and stopping on the buried buffer layer 2 (cf. FIG. 8). Thebuffer layer 2 is then removed with a wet method and the first bondingoxide layer 13 is etched. A marking 16 is thereby made at the same placeas the marking 8 (cf. FIG. 9).

The silicon layer 3 and the inside of the marking 16 are thensuccessively covered with a second gate oxide layer 17, with a secondpattern layer 18 and with a resin layer 19 (cf. FIG. 10). As it willappear below, the pattern layer 18 is the layer in which the secondpattern is formed. An optical or electronic lithography step then allowsthe location 20 of a second gate to be defined relatively to the marking16. As the marking 16 is made at the same place as the marking 8, thelocation of the second gate is thereby aligned with the location of thefirst gate. The resin layer 19 and the second pattern layer 18 are thenetched, for example, by plasma etching, in order to make the second gate22 covered with a resin layer 21 (cf. FIG. 11).

FIGS. 12 and 13 illustrate an alternative method of method illustratedin FIGS. 1-11.

According to this alternative, during the formation of the secondmarking 16, the latter is transferred into the transfer substrate 15, asthis appears in FIG. 12. The thin silicon film 3 is then used as a maskto anisotropic etching of the oxide by a plasma, selectively to silicon.Next, the oxide defines a mask for the anisotropic etching of thesilicon of the transfer substrate, the B portion on which the gate ismade, being protected with a resin layer 23 during this step (cf. FIG.13).

FIGS. 14-20 illustrate different steps of a second embodiment of themethod for aligning patterns according to the invention. According tothis second embodiment, formation of the first marking is carried outbefore depositing the first pattern layer.

The starting structure then consists of the substrate 1, the bufferlayer 2 and the thin layer 3 (cf. FIG. 14). A resin layer 24 is first ofall deposited on the thin layer 3 and etching the resin layer 24 causesthe position 25 of the first marking to appear (cf. FIG. 15). The thinlayer 3 and the buried buffer layer 2 are etched in order to form thefirst marking 26 (cf. FIG. 16). The resin layer 24 is then suppressedand a gate oxide layer 27, a first pattern layer 28 and a resin layer 29are successively deposited on the structure obtained after forming thefirst marking 26 (cf. FIG. 17). An optical electronic lithography stepallows the location 31 of a first gate to be defined (cf. FIG. 17).During the lithography step, the location 31 of the first gate isaligned on the marking 26. A first gate 32 covered with a resin layer33, is then formed (cf. FIG. 18). The resin layer 33 is then removed anda first bonding oxide layer 34 is deposited and flattened (cf. FIG. 19).The obtained structure is then turned over and the free face of thelayer 34 is bonded by molecular bonding (oxide on oxide) onto a secondbonding oxide layer 14 which covers a transfer substrate 15 (cf. FIG.20).

The formation of the second marking is then carried out as illustratedin FIGS. 8-11, with also the alternative relative to the transfer of thesecond marking in the transfer substrate, as illustrated in FIGS. 12 and13. The illustrative figures of the formation of the second marking andof the transfer of the second marking in the transfer substrate have notbeen illustrated in order not to make the description needlesslycomplicated.

An advantage of the second embodiment of the invention is thepossibility of using the first marking for making patterns both in thethin film and in the first pattern layer. It is then possible to gainprecision in aligning patterns relatively to each other. As anon-limiting example, in the case when the pattern in the thin film is atransistor active area and when the first pattern layer is the gatelayer of the transistor, by gaining precision in alignment, the accessresistors may be reduced notably in the case of narrow transistors,since it is then possible to reduce the margin on the dimensions of theactive area which is very resistive.

1. A method for forming patterns aligned on either side of a thin filmdeposited on a substrate, the method comprising local etching of thethin film in order to form a first marking characterized in that itcomprises: depositing a first pattern layer on the thin film, depositionof the first pattern layer preceding or following local etching of thethin film, a first lithography step for defining a location of a firstpattern, with alignment of the first pattern location relatively to thefirst marking, local etching of the first pattern layer in order to forma first pattern, depositing a first bonding layer for covering the firstmarking and the first pattern, turning over the obtained structurefollowing the deposition of the first bonding layer, suppressing thesubstrate, a step for etching the first bonding layer in order to form asecond marking at the location of the first marking, a step fordepositing a second pattern layer, a second lithography step fordefining a location of a second pattern, with alignment of the secondpattern location relatively to the second marking, and a step foretching the second pattern layer in order to form the second pattern. 2.The method for forming patterns according to claim 1, characterized inthat the turning over of the structure is followed by a bonding step forbonding the first bonding layer with a second bonding layer which coversa transfer substrate.
 3. The method according to claim 2, characterizedin that, as the first and second bonding layers are oxide layers,bonding is a molecular bonding.
 4. The method according to claim 2,characterized in that the second marking is transferred into thetransfer substrate.
 5. The method according to claim 1, characterized inthat the local etching of the first and second pattern layers is plasmaetching.
 6. The method according to claim 1, characterized in that thefirst and the second pattern layers are layers of polycrystallinesilicon, or metal, or nitride or silicon, or silica.
 7. The methodaccording to claim 1, characterized in that the thin film issemiconductor thin film.
 8. The method according to claim 7,characterized in that the semiconductor thin film is silicon, galliumarsenide, or SiGe film.
 9. The method according to claim 7,characterized in that the local etching of the semiconductor thin filmis wet chemical etching or anisotropic plasma etching.
 10. The methodaccording to claim 7, characterized in that it comprises a step forforming a first gate oxide layer between the semiconductor thin film andthe first pattern layer and in that the step for depositing the secondpattern layer is preceded by the deposition of a second gate oxide layeron the semiconductor thin film.
 11. The method according to claim 10,characterized in that the first pattern and the second pattern aretransistor gates.
 12. The method according to claim 1, characterized inthat the thin film is a metal thin film.
 13. The method according claim12, characterized in that the metal thin film is TiN or W film.
 14. Themethod according to claim 1, characterized in that the first and secondlithography steps are optical or electronic lithography steps.
 15. Themethod according to claim 1, characterized in that it comprises theformation of a buried buffer layer between the thin film and thesubstrate.
 16. The method according to claim 15, characterized in thatthe buried buffer layer is a SiO₂ or SiGe layer.